This application claims priority from Korean Patent Application No. 2003-23969, filed on Apr. 16, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a transistor and a method of manufacturing the same. More particularly, the present invention relates to a schottky barrier transistor (referred to as “SB transistor”, hereinafter) using a schottky barrier formed between a metal and a semiconductor, and a method of manufacturing the same.
2. Description of the Related Art
Semiconductor device fabrication technology has reached the level where it is now possible to fabricate transistors that have a short channel with a length less than 100 nm. However, integration simply by reduction in transistor size causes various problems. The most important issues are a short channel effect (SCE) due to the scaling-down of devices and a source/drain doping associated with a decrease in source/drain resistance.
In particular, the formation of a source/drain by ion implantation in a conventional transistor fabrication method is accompanied by the following problems. First, it is difficult to adjust the depth of a junction. Since diffusion of impurities occurs both in depth and channel directions, it is difficult to prevent a short channel effect. In this regard, rapid thermal process (RTP), laser annealing, solid phase diffusion (SPD), and the like have been suggested as an alternative to ion implantation. However, a channel depth of less than 10 nm for prevention of a short channel effect is difficult to attain. Second, a saturation current is unavoidably reduced. That is, as devices become more integrated, a junction becomes thinner and a sheet resistance increases, thereby reducing the saturation current. Third, high-temperature thermal treatment above 800° C. is required for activation of impurities implanted in a source/drain. Therefore, a metal gate cannot be used. Fourth, a soft error rate at a junction interface is high and a floating body effect may be caused.
In order to solve these problems, SB transistor fabrication technology using metal suicide as a material for a source/drain has been suggested. According to this technology, since problems due to source/drain doping are not caused, a source/drain resistance can be greatly reduced. In addition, a high-temperature thermal treatment process can be omitted. Therefore, this technology is compatible with a process of using a metal as a gate electrode for satisfying low power consumption/rapid processing speed of devices.
In a conventional SB transistor fabrication method, a source/drain is formed by heating a deposited metal to induce silicidation and then removing an unreacted metal by selective wet etching. The silicidation and the selective wet etching are generally known as a salicide process. However, since interest in using SB transistors as alternatives to nanoelectronic devices have been raised just recently, optimization of the structure and fabrication process of the SB transistors has still not been established. In this regard, there are needs to efficiently adjust a schottky barrier height, which greatly affects device characteristics, and at the same time, to optimize a fabrication process for ultra-small devices.
In particular, one important and difficult process in the SB transistor fabrication method is selective wet etching for removing only an unreacted metal. The degree of difficulty of the selective wet etching varies depending on the types of metals and the etching patterns. However, use of noble metals and formation of a fine pattern increase the difficulty of the selective wet etching.
Another important and difficult process in the SB transistor fabrication method is etching damage removal. In the SB transistors, interface characteristics between a metal silicide layer and a silicon substrate are very important. Etching damage caused during a formation of a spacer on a sidewall of a gate is a main factor that adversely affects the interface characteristics between the metal silicide layer and the silicon substrate. Until now, there have been no efficient solutions to the etching damage.